This invention relates to the design of IP (Intellectual Property), and more particularly to a synchronizing circuit which enables an exchange of signals between an IP functional circuit and a system bus using two types of clocks: a local clock for driving the IP functional circuit built in an LSI and a system clock for driving the system bus.
Furthermore, the present invention integrates the IP functional circuit and the synchronizing circuit into an entity and uses the resulting circuit as an IP (functional block) in the design of an LSI. The invention includes a semiconductor integrated circuit containing the IP functional circuit and synchronizing circuit.
Using FIG. 1, conventional IP designs will be explained. Some of the conventional IP designs depend on the system bus and the others do not depend on the system bus. FIG. 1 shows an example of an IP design depending on the system bus. Numeral 1 indicates the system bus for transmitting the input and output signals of an IP. The system bus operates in synchronization with a system clock. Numeral 2 indicates an IP to be designed, which operates in synchronization with the system clock and local clock.
In the conventional IP design shown in FIG. 1, since the IP 2 itself is designed dependently on a specific system bus 1, the IP 2 can be used as it is, regardless of the difference in frequency between the system clock and local clock, in reusing the IP 2 for 94 the design of an LSI with a specific system bus 1.
Because the IP vendor must prepare a separate IP for each of the various system buses, this decreases the efficiency of the IP vendor. To avoid this, an IP design independent of the system bus as shown in FIG. 2 has been used.
In FIG. 2, IP 3 indicates a circuit which synchronizes with only the local clock and which is connected to the system bus 1 via a bridge block 4 that absorbs the difference between the system clock and local clock. Specifically, a circuit 5 composed of the IP 3 and the bridge block 4 is connected to the system bus 1 synchronizing with the system clock.
The bridge block is a circuit block which enables signal exchange between the IP bus synchronizing with the local clock and the system bus synchronizing with the system clock and which includes a circuit that synchronizes with both of the local clock and system clock.
As shown by vertical broken lines and single-dash-dot lines in FIG. 3, the rising or falling edges of the local clock generally containing a plurality of clocks have to be synchronized with the system clock in various modes. Because the duration time of the high level or low level of the local clock has to be set to a different length according to the function of the IP, the design of a bridge block is complex.
The bridge block is developed by the IP reuser. Therefore, in the conventional IP design using a bridge block, since the bridge block absorbs the difference between clocks, this imposes on the IP reuser the heavy burden of developing a complex circuit constituting a bridge block, which causes the problem of lengthening the time required for development.
As described above, in the conventional IP design, IP design dependent on the system bus requires the IP vendor to prepare an IP corresponding to each of the various system buses, whereas IP design independent of the system bus causes the problem of imposing on the IP reuser the heavy burden of developing a complex bridge block for absorbing the difference between the system clock and local clock.